learn_riscv/README.md

# Hello RISCV 

To develop on your x86_64 desktop PC you need QEMU and the GNU riscv compiler toolchain.

```
sudo apt-get install qemu qemu-system-misc gcc-riscv64-linux-gnu sudo apt install gcc-riscv64-unknown-elf
```



## Checking your toolchain

If you are building binaries to target a Linux system:
```
riscv64-linux-gnu-as --version
```

For building standalone Executable and Linkable Format (ELF) binaries that are not tied to any specific operating system use:

```
riscv64-unknown-elf-as --version
```

The output object files are lined against a bare-metall environment or an embedded system that does not rely on an OS. Might use Newlib or another lightweight C lib instead of glibc. Good for embedded systems, bootloaders, or bare metal apps that have no operating system.

### The typical build workflow

You will want to know the following two(three) values for your build target:

-`march=ISA` selects the architecture to target. This controls which instructions and registers are available for the compiler to use. Describes which hardware generated code can run on
-`mabi=ABI` selects the ABI to target. This controls the calling convention (which arguments are passed in which registers) and the layout of data in memory. Describes which software generated code can link against. In order for objects to be linked together, they must follow the same ABI.
    - ilp32: int, long, and pointers are all 32bits, long is a 64 bit type, char 8 bit, short 16 bit. No floating point registers.
    - lp64: long and pointers are 64 bits long, while int is 32 bit type. The other types remain the same as ilp32
    - ilp32f: Same as ipl32 but with 32 bit and smaller floating point arguments are passed in registers. This ABI requires the F extension.
    - ilp32d: 64 bit and smaller floating point arguments,are passed in registers. ABI requires the D extension.
    - etc.
-`mtune=CODENAME` selects the microarchitecture to target. This informs GCC about the performance of each instruction, allowing it to perform target-specific optimizations. Most times you will not need to use this argument.

See: [The -march, -mabi, and -mtune arguments to RISC-V Compilers](https://www.sifive.com/blog/all-aboard-part-1-compiler-args) for more detail.

Example: If our target has integer, multiplication, atomic memory operations, and compressed instructions extensions then our assembler command would look like:

```
riscv64-linux-gnu-as -march=rv32imac -mabi=ilp32 ...
```


## Using QEMU

Ensure it's installed

```
qemu-system-riscv --version
```

```
qemu-system-riscv32 -machine help
Supported machines are:
none                 empty machine
opentitan            RISC-V Board compatible with OpenTitan
sifive_e             RISC-V Board compatible with SiFive E SDK
sifive_u             RISC-V Board compatible with SiFive U SDK
spike                RISC-V Spike board (default)
virt                 RISC-V VirtIO board
toor@toor-jammy-jellifish:~/experiments/learn_r
```

We are going to focus on the `virt` machine type.

See ./chuckstechtalk/hello_asm/README.md for more fantastic QEMU details.

## Resources

- [RISC-V Instruction Set Manual](https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf)
- [Linux Kernel system calls for all architectures](https://gpages.juszkiewicz.com.pl/syscalls-table/syscalls.html)
- [RISC-V ASM Manual](https://github.com/riscv-non-isa/riscv-asm-manual/blob/main/riscv-asm.md)
- [Sample RISC-V ASM Programs](https://marz.utk.edu/my-courses/cosc230/book/example-risc-v-assembly-programs/)
- [RISC-V Assembly Programming](https://riscv-programming.org/) Includes a book, exercises, and a simulator
- [The -march, -mabi, and -mtune arguments to RISC-V Compilers](https://www.sifive.com/blog/all-aboard-part-1-compiler-args)