diff --git a/devices/lirc/lirc.go b/devices/lirc/lirc.go
index 8dbc123..1233709 100644
--- a/devices/lirc/lirc.go
+++ b/devices/lirc/lirc.go
@@ -21,9 +21,10 @@ import (
 
 // Conn is an open port to lirc.
 type Conn struct {
-	w           net.Conn
-	c           chan ir.Message
-	lock        sync.Mutex
+	w net.Conn
+	c chan ir.Message
+
+	mu          sync.Mutex
 	list        map[string][]string // list of remotes and associated keys
 	pendingList map[string][]string // list of remotes and associated keys being created.
 }
@@ -66,8 +67,8 @@ func (c *Conn) Channel() <-chan ir.Message {
 //
 // Empty if the list was not retrieved yet.
 func (c *Conn) Codes() map[string][]string {
-	c.lock.Lock()
-	defer c.lock.Unlock()
+	c.mu.Lock()
+	defer c.mu.Unlock()
 	return c.list
 }
 
@@ -176,10 +177,10 @@ func (c *Conn) readData(r *bufio.Reader) error {
 					}
 				}
 				if all {
-					c.lock.Lock()
+					c.mu.Lock()
 					c.list = c.pendingList
 					c.pendingList = nil
-					c.lock.Unlock()
+					c.mu.Unlock()
 				}
 			}
 		default:
diff --git a/experimental/devices/bitbang/i2c.go b/experimental/devices/bitbang/i2c.go
index f1c6388..2a3fdd1 100644
--- a/experimental/devices/bitbang/i2c.go
+++ b/experimental/devices/bitbang/i2c.go
@@ -25,7 +25,7 @@ const SkipAddr uint16 = 0xFFFF
 
 // I2C represents an I²C master implemented as bit-banging on 2 GPIO pins.
 type I2C struct {
-	lock      sync.Mutex
+	mu        sync.Mutex
 	scl       gpio.PinIO // Clock line
 	sda       gpio.PinIO // Data line
 	halfCycle time.Duration
@@ -42,8 +42,8 @@ func (i *I2C) Close() error {
 
 // Tx implements i2c.Conn.
 func (i *I2C) Tx(addr uint16, w, r []byte) error {
-	i.lock.Lock()
-	defer i.lock.Unlock()
+	i.mu.Lock()
+	defer i.mu.Unlock()
 	runtime.LockOSThread()
 	defer runtime.UnlockOSThread()
 	//syscall.Setpriority(which, who, prio)
@@ -90,8 +90,8 @@ func (i *I2C) Tx(addr uint16, w, r []byte) error {
 
 // Speed implements i2c.Conn.
 func (i *I2C) Speed(hz int64) error {
-	i.lock.Lock()
-	defer i.lock.Unlock()
+	i.mu.Lock()
+	defer i.mu.Unlock()
 	i.halfCycle = time.Second / time.Duration(hz) / time.Duration(2)
 	return nil
 }
diff --git a/experimental/devices/bitbang/spi.go b/experimental/devices/bitbang/spi.go
index 11601d7..b7ebac4 100644
--- a/experimental/devices/bitbang/spi.go
+++ b/experimental/devices/bitbang/spi.go
@@ -24,11 +24,12 @@ import (
 
 // SPI represents a SPI master implemented as bit-banging on 3 or 4 GPIO pins.
 type SPI struct {
-	sck       gpio.PinOut // Clock
-	sdi       gpio.PinIn  // MISO
-	sdo       gpio.PinOut // MOSI
-	csn       gpio.PinOut // CS
-	lock      sync.Mutex
+	sck gpio.PinOut // Clock
+	sdi gpio.PinIn  // MISO
+	sdo gpio.PinOut // MOSI
+	csn gpio.PinOut // CS
+
+	mu        sync.Mutex
 	mode      spi.Mode
 	bits      int
 	halfCycle time.Duration
@@ -45,16 +46,16 @@ func (s *SPI) Close() error {
 
 // Speed implements spi.Conn.
 func (s *SPI) Speed(hz int64) error {
-	s.lock.Lock()
-	defer s.lock.Unlock()
+	s.mu.Lock()
+	defer s.mu.Unlock()
 	s.halfCycle = time.Second / time.Duration(hz) / time.Duration(2)
 	return nil
 }
 
 // Configure implements spi.Conn.
 func (s *SPI) Configure(mode spi.Mode, bits int) error {
-	s.lock.Lock()
-	defer s.lock.Unlock()
+	s.mu.Lock()
+	defer s.mu.Unlock()
 	if mode != spi.Mode3 {
 		return errors.New("not implemented")
 	}
@@ -72,8 +73,8 @@ func (s *SPI) Tx(w, r []byte) error {
 	if len(r) != 0 && len(w) != len(r) {
 		return errors.New("write and read buffers must be the same length")
 	}
-	s.lock.Lock()
-	defer s.lock.Unlock()
+	s.mu.Lock()
+	defer s.mu.Unlock()
 	if s.csn != nil {
 		s.csn.Out(gpio.Low)
 		s.sleepHalfCycle()