/*
This allocates the counter variable in RAM
As you can see in the Watch1 window after watching the
counter variable and we see indeed in is stored at 0x20000000
address in memory

Looping through the dissassembly we now see that LDR.N instruction
is being used to increment the value as opposed to the ADD instruction
Looking at R0 we can see that the value is storing 0x20000000
So R0 is referencing our int stored in RAM

LDR.N means load the Register from memory
The STR instruction is used here to save the value of R1 to the
memory location reference in R0.


An Arm processor is a Reduced Instruction Set Computer (RISC) Architecture
Memory can be only read by the special load instructions (e.g. LDR, LDR.N)
with data manipulations occuring only in the registers. Finally, the modified
register values can be stored back into memory using the store instuctions (STR)

This is in contrast to the Complex Instruction Set Computer (CISC) that make up
instruction sets like the x86 where some of the complex operands can be operated
on directly in memory.

Take note that using the *p_int pointer simplifies the instructions produced by
the compiler. Instead of multiple calls to LDR.N and STR to load and store our
counter we instead load it once then operate directly o

*/

int counter = 0;


int main(){
    // locations in memory can be stored in pointers
    int *p_int;
    // The operator & gives the address of the counter variable assigning it to
    // p_int.
    p_int = &counter;
    // To get the value stored at that memory location we must derefence it with
    // the * operator. *p_int then means the valu
    while (*p_int < 30){ 
        ++(*p_int);
    }
    return 0;
}